comtech aha corporation 2345 ne hopkins court pullman wa 99163 tel: 509.334.1000 fax: 509.334.9000 www.aha.com a subsidiary of comtech telecommunications corporation psfecdecodercore_0702 product specification aha g.709-2.5 fec decoder core
comtech aha corporation psfecdecodercore_0702 a subsidiary of comtech telecommunications corporation i table of contents 1.0 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 reed solomon code parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3.0 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3.1 input interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3.2 output interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4.0 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
comtech aha corporation ii a subsidiary of comtech telecommunications corporation psfecdecodercore_07021 list of figures figure 1: block diagram: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2: input interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 3: output interface timing, start of output transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 4: output interface timing, end of output transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
comtech aha corporation psfecdecodercore_0702 a subsidiary of comtech telecommunications corporation page 1 of 4 1.0 introduction this g709d-2.5 core is specifically designed to efficiently perform the reed-solomon decoding function specified by the itu g.709 standard. the core requires no configuration, no initialization, and no re-synchronization procedure or includes any unnecessary features that would add area, power, or complexity to your design. 1.1 features performance: ? 2.5 gbits/sec operation in .13 micron cmos process ? 40 k gates in .13 micron using a typical standard cell library ? 332 mhz clock at 2.5 gbits/sec ? 8 bit input and output data interfaces ? complete error reporting for bit error rate calculation and feedback into threshold detection circuits flexibility: ? one-edge, one-clock fully synchronous design without multi-cycle paths ? supports both streaming of data and gaps between blocks ? separate fifo for increased flexibility and simplified ic floor planning ? 319 clock latency through the core (1 block + 64 clocks) deliverables: ? g.709d-2.5 fec core (vhdl) ? timing constraints (designcompiler and ambit format) ? test bench and verification vectors (vhdl) ? single use license of aha?s reed-solomon patents pat ent s: ? design uses one or more of the following us patents: 5,170,399; 5,099,482; 4,873,688; 5,396,502 2.0 functional description figure 1: block diagram: 2.1 decoding the core implements a g.709d reed-solomon code (255,239) decoder. this code is capable of correcting up to 8 (t = 8) byte-errors in a 255-byte block. the core has two phases of operation, a data input phase and a data correct phase. during the data input phase the block data is read one byte at a time. the data coming in on this phase is not stored internal to the core, but is stored in the external fifo. this phase takes 255 clocks. the data correct phase requires 64 clocks after the last byte of the block is read to begin to output the corrected data. the original data is read from the fifo, corrected and output. the first byte of a block is received with a start signal. fifo data is required to start arriving 317 clocks later. the block is output when the data valid signal is asserted. decode_complete will assert with the first transfer. two clocks after the block is output the status valid signal asserts indicating that the correction count signals and the uncorrectable signal are valid. correct_to_zero[7:0] correct_to-one[7:0] status_valid decode_complete uncorrectable decoded_data[7:0] clk reset start received_data[7:0] fifo, 3k bits fifo_data[7:0] ahag709d-2.5 fec
comtech aha corporation page 2 of 4 a subsidiary of comtech telecommunications corporation psfecdecodercore_0702 2.2 reed solomon code parameters generator polynomial: where is a root of the binary primitive polynomial x 8 + x 4 + x 3 + x 2 + 1. parity bytes are represented by: where r j (j = 0 to 15) is the parity byte represented by an element out of gf(256) and r 15 corresponds to the byte 240 in the fec sub-row and r 0 to byte 255. 3.0 signal descriptions 3.1 input interface gz () z i ? () i 0 = 15 = rz () r 15 z 15 r 14 z 14 r 1 z 1 r 0 + ? + ? + ? = signal type description clk i system clock. 332 mhz core clock. all inputs are registered on the rising edge. reset i system hard reset. assertion of this signal will cause loss of all data currently in the core. reset must remain active for 3 clocks. received_data[7:0] i data input. data is registered on the rising edge of clk every clk. a block is received one byte at a time. start i block start signal. this signal is asserted with the first transfer of a block. start signals should be at least 255 clocks apart, but can be more then 255 clocks apart. this signal should be deasserted during all other clocks. fifo_data[7:0] i fifo data. delayed version of the received_data data stream. this signal is delayed 317 clocks.
comtech aha corporation psfecdecodercore_0702 a subsidiary of comtech telecommunications corporation page 3 of 4 3.2 output interface 4.0 timing diagrams figure 2: input interface timing signal type description decode_complete o decoding complete. active when the first byte of the g.709 frame is on the decode_data data bus and is inactive on all subsequent transfers. decoded_data[7:0] o decoded data. a block is transferred out one byte at a time. the first byte is available when decode_complete is asserted. status_valid o status valid signal. active for a single clk two clks following the completion of the frame to indicate when the uncorrectable, correct_to_zero and correct_to_one signals are valid uncorrectable o uncorrectable block flag. valid when status_valid is asserted. when asserted the block is not correctable. correct_to_zero[7:0] o number of bits corrected from ?1? to ?0? in the block. valid when status_valid is asserted. correct_to_zero[7:0] o number of bits corrected from ?0? to ?1? in the block. valid when status_valid is asserted. x1 2 3 4 5 6 clk reset start received_data
comtech aha corporation page 4 of 4 a subsidiary of comtech telecommunications corporation psfecdecodercore_0702 figure 3: output interface timing, start of output transfer figure 4: output interface timing, end of output transfer clk status_valid x x x x x x x x x x x x x x x x x x uncorrectable fifo_data correct_to_zero decoded_data correct_to_one decode_complete x1 2 3 4 5 6 7 8 23 4 5 6 7 8 910 clk x decode_complete x x x x x x x correct_to_zero decoded_data correct_to_one status_valid 0 x xxx 255 254 253 252 x x x x x x x x 0 x uncorrectable
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